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1 pi6c20800b features ? ? 4 lvpecl outputs ? ? up to 1.5ghz output frequency ? ? ultra low additive phase jitter: < 0.04 ps (typ) ? ? two selectable inputs ? ? low delay from input to output (tpd typ. < 1.0ns) ? ? 2.5v / 3.3v power supply ? ? industrial temperature support ? ? tssop-20 package p i 6 c 49115 0 4 - 01 block diagram pin confguration (20-pin tssop) description te PI6C4911504-01 is a high performance fanout bufer device which supports up to 1.5ghz frequency. tis device is ideal for systems that need to distribute low jitter clock signals to mul - tiple destinations. applications ? ? networking systems including switches and routers ? ? high frequency backplane based computing and telecom platforms high performance lvpecl fanout buffer q0+ pullup in_sel ref_in0+ ref_in0- d le q sync_oe pulldown pullup 0 1 pulldown q0- q1+ q1- q2+ q2- q3+ q3- ref_in1+ ref_in1- pulldown pullup 1 2 3 ref_in0+ 4 ref_in0- 5 in_sel 6 ref_in1- 7 v dd 8 ref_in1+ q0+ v dd q1+ q2+ q2- nc 20 19 18 17 16 15 14 13 gnd sync_oe q1- q0- q3+ 9nc 12 q3- 10v dd 11 www.pericom.com pi6c491 1504-01 rev a 2/27/15 15-0027
2 function table table 1: clock source input select function in_sel function 0 ref_in0 is the selected reference input 1 ref_in1 is the selected reference input table 2: sync_oe select function sync_oe function 0 all outputs disabled. q+ disabled low, q- disabled high. 1 all outputs enabled. pin characteristics symbol parameter min ty p max units r pullup input pullup resistor 50 k r pulldown input pulldown resistor 75 k pin # pin name ty pe description 1 gnd power ground 2 sync_oe input pullup synchronous clock enable. when high, clock outputs follow ref_in. when low, q+ outputs are forced low, q- are forced high 3 in_sel input pulldown clock input source selection pin 4, 5 ref_in0+ ref_in0- input pulldown pullup diferential clock input 0 6, 7 r ef_in1+ ref_in1- input pulldown pullup diferential clock input 1 8, 9 nc - no connect 10, 13, 18 v dd power power supply 11, 12 q3+ q3- output lvpecl output clock 3 14, 15 q2+ q2- output lvpecl output clock 2 16, 17 q1+ q1- output lvpecl output clock 1 19, 20 q0+ q0- output lvpecl output clock 0 pinout table www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
3 power supply characteristics and operating conditions symbol parameter test condition min. ty p. max. units v dd supply voltage 3.135 3.465 v 2.375 2.625 v i dd power supply current outputs unloaded 90 ma t a ambient operating temperature -40 85 c maximum ratings (above which the useful life may be impaired. for user guidelines, not tested) storage temperature ................................................... - 55 to +150oc s upply voltage to ground potential (v dd ) ........... - 0.5 to +4.65v inputs (referenced to gnd) ............................. -0.5 to v dd +0.5v c lock output (referenced to gnd)................. -0.5 to v dd +0.5v s oldering temperature (max of 10 seconds) .................... +260oc latch up .................................................................................. 200ma esd protection (input) .................................. 2000 v min (hbm) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. lvcmos/ lvttl dc characteristics symbol parameter test condition min. ty p. max. units v ih input high voltage v dd = v in = 3.465v 2 v dd +0.3 v v dd = v in = 2.625v 1.6 v dd +0.3 v v il input low voltage v dd = v in = 3.465v -0.3 0.8 v v dd = v in = 2.625v -0.3 0.6 v i ih input high current sync_oe v dd = v in = 3.465v 5 a v dd = v in = 2.625v 5 in_sel v dd = v in = 3.465v 150 a v dd = v in = 2.625v 150 i il input low current sync_oe v dd = v in = 3.465v -150 a v dd = v in = 2.625v -150 in_sel v dd = v in = 3.465v -5 a v dd = v in = 2.625v -5 www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
4 dc electrical specifcations- lvpecl outputs parameter description conditions min. ty p. max. units v oh output high voltage v dd = 3.3v 5% v dd -1.4 v dd -0.9 v v dd = 2.5v 5% v dd -1.6 v dd -0.8 v v ol output low voltage v dd = 3.3v 5% v dd -2.0 v dd -1.6 v v dd = 2.5v 5% v dd -2.0 v dd -1.5 v parameter description conditions min. ty p. max. units f out clock output frequency lvpecl 1500 mhz t r output rise time from 20% to 80% 300 400 600 ps t f output fall time from 80% to 20% 300 400 600 ps t odc output duty cycle frequency<650mhz 48 52 % v pp output swing single-ended frequency<650mhz 400 t addjitter bufer additive jitter rms using 156.25mhz xo, 0.17ps jitter as source @3.3v 0.05 ps t phasejitter total output jitter rms using 156.25mhz xo, 0.17ps jitter as source @3.3v 0.23 ps t sk output skew 4 outputs devices, outputs in same tank, with same load, at dut. 40 ps t pd propagation delay 1000 ps t od valid to hiz 100 ns t oe hiz to valid 100 ns ac electrical specifcations C differential outputs notes: 1. tis parameter is guaranteed by design dc electrical specifcations - differential inputs symbol parameter min. ty p. max. units i ih input high current ref_in- input = v dd 5 a ref_in+ input = v dd 150 a i il input low current ref_in- input = gnd -150 a ref_in+ input = gnd -5 a v id input diferential amplitude (vp-p) 0.15 v dd -2.0 v v cm common mode input voltage ref_in0 0.5 v dd -0.85 v ref_in1 1.5 v dd www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
5 phase noise plots f out = 156.25mhz output phase noise (dark blue) vs input phase noise (light blue) additive jitter is calculated at 156.25mhz~40fs rms (12khz to 20mhz). additive jitter = (output jitter 2 - input jitter 2 ) www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
6 confguration test load board termination for lvpecl v 100 150 z = 50 l = 0 ~ 10in 150 device o z = 50 o dd tla tla www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
7 application information suggest for unused inputs and outputs lvcmos input control pins it is suggested to add pull-up=4.7k and pull-down=1k for lvc - mos pins even though they have internal pull-up/down but with much higher value (>=50k) for higher reliability design. diferential +in/-in input pins tey can be lef foating if not used. connect them 1k to gnd is optional for the additional protection. outputs all unused outputs are suggested to be lef open and not con - nected to any trace. tis can lower the ic power supply power. power decoupling & routing vdd pin decoupling as general design rule, each vdd pin must have a 0.1uf decou - pling capacitor. for better decoupling, 1uf can be used. locat - ing the decoupling capacitor on the component side has better decoupling flter result as shown below. placement of decoupling caps diferential clock trace routing always route diferential signals symmetrically, make sure there is enough keep-out space to the adjacent trace (>20mil.). in 156.25mhz xo drives ic example, it is better routing diferen - tial trace on component side as the following. clock ic device 2 ref_in - ref_in+ 3 4 5 6 vdd gnd keep out board vias vcc gnd 150 150 156.25m xo 0.1uf *100 *100 is optional if ic has gnd ic routing for xo drive clock ic device vdd 11 13 10 9 8 12 14 0.1uf 0.1uf gnd gnd vdd vdd decouple cap. on comp. side gnd clock timing is the most important component in pcb design, so its trace routing must be planned and routed as a frst prior - ity in manual routing. some good practices are to use minimum vias (total trace vias count <4), use independent layers with good reference plane and keep other signal traces away from clock traces (>20mil.) etc. www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
8 lvpecl and lvds input interface lvpecl and lvds dc/ ac input lvpecl and lvds clock input to this ic is connected as shown below. lvpecl/ lvds input cmos clock dc drive input lvcmos clock has voltage voh levels such as 3.3v, 2.5v, 1.8v. cmos drive requires a vcm design at the input: vcm= ? (cmos v) as shown below 7. rs =22 ~33ohm typically. cmos dc input vcm design www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
9 device lvpecl output terminations lvpecl output popular termination te most popular lvpecl termination is 150ohm pull-down bias and 100ohm across at rx side. please consult asic data - sheet if it already has 100ohm or equivalent internal termina - tion. if so, do not connect external 100ohm across as shown in below. tis popular terminations advantage is that it does not allow any bias through from vcc. tis prevents vcc system noise coupling onto clock trace. lvpecl output tevenin termination figure below shows lvpecl output tevenin termination which is used for shorter trace drive (<5in.), but it takes vcc bias current and vcc noise can get onto clock trace. it also requires more component count. so it is seldom used today. lvpecl output popular termination lvpecl tevenin output termination lvpecl output ac tevenin termination lvpecl ac tevenin terminations require a 150ohm pull- down before the ac coupling capacitor at the source as shown below. note that pull-up/down resistor value is swapped com - pared to previous fgure. tis circuit is good for short trace (<5in.) application only. lvpecl output drive hcsl input using the lvpecl output to drive a hcsl input can be done using a typical lvpecl ac tenvenin termination scheme. use pull-up/down 450/60ohm to generate vcm=0.4v for the hcsl input clock. tis termination is equivalent to 50ohm load as shown. lvpecl output drive hcsl termination lvpecl output ac tenvenin termination www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
10 lvpecl output v_swing adjustment it is suggested to add another cross 100ohm at tx side to tune the lvpecl output v_swing without changing the optimal 150ohm pull-down bias. tis form of double termination can reduce the v_swing in ? of the original at the rx side. by fne tuning the 100ohm resistor at the tx side with larger values like 150 to 200ohm, one can increase the v_swing by > 1/2 ratio. lvpecl output v_swing adjustment lvpecl v_swing adjustment using rs another way to control v_swing is by adding serial rs. rs value is tunable between 22 to 33 ohm depending on application. tis method may reduce the clock drive pcb trace in slower tr/tf . lvpecl v_swing adjustment using rs clock jitter defnitions total jitter= rj + dj random jitter (rj) is unpredictable and unbounded timing noise that can ft in a gaussian math distribution in rms. rj test val - ues are directly related with how long or how many test samples are available. deterministic jitter (dj) is timing jitter that is pre - dictable and periodic in fxed interference frequency. total jitter (tj) is the combination of random jitter and deterministic jitter: , where is a factor based on total test sample count. jedec std. specifes digital clock tj in 10k random samples. phase jitter phase noise is short-term random noise attached on the clock carrier and it is a function of the clock ofset from the car - rier, for example dbc/hz@10khz which is phase noise power in 1-hz normalized bandwidth vs. the carrier power @10khz ofset. integration of phase noise in plot over a given frequency band yields rms phase jitter, for example, to specify phase jitter <=1ps at 12k to 20mhz ofset band as sonet standard specif - cation. pcie ref_clk jitter pcie reference clock jitter specifcation requires testing via the pci-sig jitter tool, which is regulated by us pci-sig organiza - tion. te jitter tool has pcie serdes embedded flter to calculate the equivalent jitter that relates to data link eye closure. direct peak-peak jitter or phase jitter test data, normally is higher than jitter measure using pci-sig jitter tool. it has high-frequency jitter and low-frequency jitter spec. limit. for more informa - tion, please refer to the pci-sig website: http://www.pcisig.com/ specifcations/pciexpress/ device thermal calculation figure below shows the jedec thermal model in a 4-layer pcb. jedec ic termal model important factors to infuence device operating temperature are: 1) te power dissipation from the chip (p_chip) is afer subtract - ing power dissipation from external loads. generally it can be the no-load device idd 2) package type and pcb stack-up structure, for example, 1oz 4 layer board. pcb with more layers and are thicker has better heat dissipation www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
11 3) chassis air fow and cooling mechanism. more air fow m/s and adding heat sink on device can reduce device fnal die junc - tion temperature tj te individual device thermal calculation formula: tj =ta + pchip x ja tc = tj - pchip x jc ja ___ package thermal resistance from die to the ambient air in c/w unit; tis data is provided in jedec model simulation. an air fow of 1m/s will reduce ja (still air) by 20~30% jc ___ package thermal resistance from die to the package case in c/w unit tj ___ die junction temperature in c (industry limit <125c max.) ta ___ ambiant air temprature in c tc ___ package case temperature in c pchip___ ic actually consumes power through iee/gnd cur - rent thermal information symbol description condition q ja junction-to-ambient thermal resistance still air 84.0 o c/w q jc junction-to-case thermal resistance 17.0 o c/w termal calculation example to calculate tj and tc of pi6cv304 in an soic-8 package: step 1: go to pericom web to fnd ja=157 c/w, jc=42 c/w http://www.pericom.com/support/packaging/packaging-me - chanicals-and-thermal-characteristics/ step 2: go to device datasheet to fnd idd=40ma max. step 3: p_total= 3.3vx40ma=0.132w step 4: if ta=85c tj= 85 + ja xp_total= 85+25.9 = 105.7c tc= tj + jc xp_total= 105.7- 5.54 = 100.1c note: te above calculation is directly using idd current without sub - tracting the load power, so it is a conservative estimation. for more precise thermal calculation, use p_unload or p_chip from device iee or gnd current to calculate tj, especially for lvpecl bufer ics that have a 150ohm pull-down and equivalent 100ohm diferential rx load. www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027
12 ordering information ordering number package code package description operating temperature PI6C4911504-01lie l pb-free & green 20-contact tssop -40 to 85 c ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? x sufx = tape/reel packaging mechanical: 20-contact tssop (l) www.pericom.com pi6c491 1504-01 rev a 2/27/15 p i 6 c 49115 0 4 - 01 high performance lvpecl fanout bufer 15-0027

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